(1) Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for fabricating the same, and more particularly relates to a nonvolatile semiconductor memory device for avoiding or suppressing damage caused by charging during processing and a method for fabricating the same.
(2) Description of Related Art
In recent years, as the memory cell size is reduced with an increase in the integration level of nonvolatile semiconductor memory devices, thinner gate electrodes serving as word lines have been suggested. However, the thinner gate electrodes make high-speed operations difficult. The reason for this is that narrower word lines increase the word-line resistances, leading to the increased delay of word-line signals.
To cope with this, it should be considered to use a self-align silicide technology (hereinafter, referred to “salicide technology”) as a measure for reducing the word-line resistances. When the salicide technology is applied to nonvolatile semiconductor memory devices, the sidewall of a gate electrode for each of memory cells need previously be covered with an insulating film to prevent shorting between a word line and a source diffusion layer or a drain diffusion layer and between a semiconductor substrate and a source diffusion layer or a drain diffusion layer.
For a memory cell of a nonvolatile semiconductor memory device, a relatively thick insulating film need usually be formed on the sidewall of a gate electrode to cope with characteristic variations and damage due to ion implantation for the formation of a source diffusion layer or a drain diffusion layer. Furthermore, in order to avoid exposing regions of a semiconductor substrate between word lines, spaces between all adjacent pairs of word lines need be completely filled with an insulating film with which the sidewall of the gate electrode is covered in accordance with the structure of a memory cell array.
Meanwhile, a nonvolatile semiconductor memory device is provided with a semiconductor device formed at a region of a semiconductor substrate outside a memory cell array region thereof. Since high performance is demanded for such a semiconductor device, it is desirable that a relatively thin insulating film is formed on the sidewall of the semiconductor device. In view of the above, it has been suggested that only the sidewall of a gate electrode serving as a word line in the memory cell array region is to be covered with a particularly thick insulating film.
As an example of a method in which the sidewall of a gate electrode serving as a word line in a memory cell array region is covered with a thick insulating film, a method for fabricating a nonvolatile semiconductor memory device according to a first known example will be described hereinafter with reference to FIGS. 16A through 18C and 19 (see, for example, Patent Document 1 (Japanese Unexamined Patent Publication No. 2003-17596)).
FIGS. 16A through 18C and 19 are cross-sectional views showing process steps in a method for fabricating the principal part of a nonvolatile semiconductor memory device according to the first known example. The method for fabricating a nonvolatile semiconductor memory device will be described hereinafter with reference to a stacked nonvolatile semiconductor memory device having a floating gate as an example of nonvolatile semiconductor memory devices. In FIGS. 16A through 18C and 19, a substrate region in which a memory cell array of a nonvolatile memory is formed is designated as a first area 100A, and a substrate region in which a semiconductor device is formed is designated as a second area 100B.
First, as shown in FIG. 16A, a p-type well region 101 is formed in the top surface of a p-type silicon substrate 100, and an isolation insulating film 102 is formed in the p-type well region 101. Thereafter, a tunnel oxide film 103 is formed on the p-type well region 101 and the isolation insulator film 102 located in both the first and second areas 100A and 100B. Next, a first polysilicon film 104 is selectively formed on the tunnel oxide film 103, and then a capacitive insulating film 105 is formed to cover the first polysilicon film 104.
Next, as shown in FIG. 16B, a first resist pattern 106 is formed to cover a part of the capacitive insulating film 105 located in the first area 100A, and etching is performed using the first resist pattern 106 as a mask. In this way, respective parts of the capacitive insulating film 105, the first polysilicon film 104 and the tunnel oxide film 103 located in the second area 100B are removed.
Next, as shown in FIG. 16C, a gate oxide film 107 is formed in the top surface of a part of the p-type well region 101 located in the second area 100B by thermally oxidizing the p-type silicon substrate 100. Thereafter, a second polysilicon film 108 is formed to entirely cover the first and second areas 100A and 100B. Although in the drawings the capacitive insulating film 105 in the first area 100A is not shown in detail, it typically has a three-layer structure (an ONO film) composed of an oxide film, a Si3N4 film, and an oxide film. In addition, although not shown for simplicity, an oxide film is formed also in the uppermost surface of the capacitive insulating film 105 in the first area 100A by thermal oxidation for the formation of the gate oxide film 107 in the second area 100B.
Next, as shown in FIG. 17A, a second resist pattern 109 is formed to cover a region of the first area 100A in which a stacked gate electrode of a nonvolatile memory is to be formed and the second area 100B, and the second polysilicon film 108, the capacitive insulating film 105, the first polysilicon film 104, and the tunnel oxide film 103 are successively etched using the second resist pattern 109 as a mask. In this way, a stacked gate electrode 108c is formed which is composed of a tunnel oxide film 103a, a floating gate electrode 104a, a capacitive insulating film 105a, and a control gate electrode 108a. In the second area 100B, the second polysilicon film 108 is patterned into a second polysilicon film 108a by etching.
Next, as shown in FIG. 17B, a third resist pattern 110 is formed to expose parts of the substrate region that will be source/drain regions of the nonvolatile memory, and n-type impurity ions are implanted (111) into the p-type well region 101 using the third resist pattern 110 and the stacked gate electrode 108c as masks. In this way, lightly-doped impurity regions 112 are formed which will become source/drain regions of the nonvolatile memory.
Next, as shown in FIG. 17C, an oxide film 113 that will partly become a sidewall insulating film of the stacked gate electrode 108c is deposited by chemical vapor deposition (CVD) to entirely cover the first and second areas 100A and 100B. Although the oxide film 113 has a thickness of, for example, about 200 nm, the thickness can be adjusted so that the sidewall insulating film formed on the sidewall of the stacked gate electrode 108c has a desired thickness.
Next, as shown in FIG. 18A, the oxide film 113 is subjected to anisotropic etching. In this way, the top surface of the stacked gate electrode 108c in the first area 100A and the top surface of the second polysilicon film 108a in the second area 100B are exposed, and first sidewall insulating films 113a are formed on the sidewall of the stacked gate electrode 108c in the first area 100A and the sidewall of the second polysilicon film 108a in the second area 100B, respectively. The above-described anisotropic etching is preferably carried out with such an etching selectivity that even if the respective top surfaces of the stacked gate electrode 108c and the second polysilicon film 108a have been exposed, the stacked gate electrode 108c and the second polysilicon film 108a are hardly etched.
Although not shown, the oxide film 113 may be subjected to anisotropic etching such that spaces between all adjacent pairs of stacked gate electrodes 108c are completely filled with first sidewall insulating films 113a formed on the sidewalls of the stacked gate electrodes 108c in accordance with the structure of a memory cell array. Furthermore, the thicknesses of the first sidewall insulating films 113a formed on the sidewalls of the stacked gate electrodes 108c can be controlled by adjusting the thickness of the oxide film 113 deposited by CVD in the process step shown in FIG. 17C.
Next, as shown in FIG. 18B, a fourth resist pattern 114 is formed to cover the first area 100A and a region of the second area 100B in which a gate electrode of a semiconductor device is to be formed, and the patterned second polysilicon film 108a and the gate oxide film 107 are etched using the fourth resist pattern 114 as a mask. In this way, a gate electrode 108b and a gate oxide film 107b for the semiconductor device are formed in the second area 100B.
Next, as shown in FIG. 18C, a fifth resist pattern 115 is formed to cover the first area 100A, and ions are implanted (116) into the second area 100B, thereby forming lightly-doped impurity regions 117 that will become a source or drain for the semiconductor device in the second area 100B.
Next, as shown in FIG. 19, an oxide film is deposited all over the first and second areas 100A and 100B by CVD and then subjected to anisotropic etching. In this way, second sidewall insulating films 118 are formed on the sidewalls of the first sidewall insulating films 113a and the sidewall of the combination of the gate electrode 108b and the gate oxide film 107b for the semiconductor device in the second area 100B. As seen from the above, a double-layer structure of the first and second sidewall insulating films 113a and 118 is formed on the sidewall of the stacked gate electrode 108c in the first area 100A. Thereafter, ions of n-type impurities are implanted (119) into the p-type well region 101 using the stacked gate electrode 108c, the gate electrode 108b, and the second sidewall insulating films 118 as masks. In this way, heavily-doped impurity regions 120a that will become a source and a drain for the nonvolatile memory are formed in the first area 100A, and heavily-doped impurity regions 120b that will become a source and a drain for the semiconductor device are formed in the second area 100B. Next, a silicide layer 121 is selectively formed on the respective top surfaces of the stacked gate electrode 108c, the gate electrode 108b and the heavily-doped impurity regions 120a and 120b using a salicide technology. Although not shown, an interlayer insulating film, contact holes and an aluminum interconnect will be formed later.
As described above, according to the method for fabricating a nonvolatile semiconductor memory device of the first known example, the sidewalls of the word lines can be covered with the sidewall insulating films of an arbitrary thickness. In addition, spaces between all adjacent pairs of the word lines can be completely filled with insulating films by adjusting the thickness of the oxide film deposited by CVD to cover the sidewalls of the word lines.
By the way, in recent years, with an increase in the integration level and processing speed of nonvolatile semiconductor memory devices, processes suitable for microprocessing, such as ion implantation or plasma-assisted dry etching, have come to be frequently used for fabrication methods for a nonvolatile semiconductor memory device. However, in these processes, charging is caused, for example, during the processing of gate electrodes.
In the fabrication method for a nonvolatile semiconductor memory device of the first known example, processes with a high possibility of charging are the ion implantation 111 shown in FIG. 17B and anisotropic etching in the formation of the first sidewall insulating films 113a by the deposition of the oxide film 113 shown in FIG. 17C and the repetition of the anisotropic etching shown in FIG. 18A.
The above-mentioned processes having a high possibility of causing charging cause the storage of excessive charges in the tunnel oxide film 103a and the capacitive insulating film 105a or damage to the tunnel oxide film 103a and the capacitive insulating film 105a. This leads to problems about the lifetime and reliability of nonvolatile semiconductor memory devices.
To cope with this, there has been suggested a method for fabricating a nonvolatile semiconductor memory device according to a second known example (see, for example, Patent Document 2 (Japanese Unexamined Patent Publication No. 11-54730)).
The fabrication method for a nonvolatile semiconductor memory device of the second known example includes the steps of: forming, around a memory array, an active region for dissipating, into a semiconductor substrate, charges to be injected into control gates corresponding to the word lines and a gate insulating film or a floating gate corresponding to the capacitive insulating film during a process for processing the control gates and the gate insulating film or the floating gate; processing the word lines and the floating gate with the control gates corresponding to the word lines connected to the active region; and disconnecting the control gates from the active region.